I. Field of the Invention
The present invention relates to a circuit and a method for providing a digital data signal with pre-distortion for transmission over a medium having frequency dependent transmission characteristics.
II. Related Art and Other Considerations
It is well known that when transmitting a signal over a frequency dependent media like a real transmission line having frequency dependent losses or an optical cable, the signal shape will change in the course of the transmission. A bandwidth limited electrical transmission line for example will cause higher losses to high frequency components of a transmitted signal than to lower frequency components. The effect of the transmission media on the signal is the more pronounced the higher the frequency components of the signal to be transmitted and the longer the transmission length through the media. This effect imposes limits on the maximum transmission length and/or the maximum speed of a signal transmission system having a signal driver at an input side of the transmission media and a receiver for receiving the signals output by the transmission media at the other side.
Modern communication systems use digital signals for carrying information. Generally speaking, a digital signal generally consists of a random sequence of so-called symbols each representing one or more data bits. When a digital signal is transmitted over a frequency dependent media like a transmission line, the transmitted digital signal will suffer from distortion even if there is perfect matching at the receiver side and at the transmitter side because the higher order harmonics in the signal spectrum suffer from higher losses than lower frequency components of the signal spectrum. Shorter pulses in the digital signal at the receiver side will not reach their full amplitude and the slope of the rising and falling edges in the signal seen by the receiver will deteriorate. This effect, also called Inter Symbol Interference (ISI), imposes limits on the data rate that the receiver will be able to detect.
As is well known, it is possible to increase the data rate or the transmission length over a given media by means of pre-distorting the digital signal at the input side of the media. Broadly speaking, the pre-distortion takes into account the distortion effected by the transmission media by means of emphasizing components of the signal to be transmitted that will suffer from loss in the transmission media. As disclosed in DE 198 25 256, a conventional way to provide a digital data signal with pre-distortion is to delay the digital signal by one bit period or a predetermined fraction of the bit period and to combine the amplitudes of the digital signal and of the delayed digital signal. From this document an output buffer circuit is known that is able to provide a digital output signal with pre-distortion by means of determining the output signal level depending not only on the current data bit to be transmitted but also dependent on the history of the output signal. U.S. Pat. No. 4,584,690 discloses minimizing the effect of intersymbol interference by provision of digital pre-compensation in the transmitted signal to maximize the slew rate between consecutive bits. From this document it is known to base the pre-compensation scheme on a knowledge of the bit pattern and the amount of energy contained in a sequence of bits.
As known e.g. from IEEE Journal of Solid State Circuits, Vol. 34 No. 5, May 1999, P. 580 to 585 a so-called full bit pre-distortion combines the amplitudes of the digital data signal with the weighted amplitudes of one or more delayed versions of the digital data signal, each delayed version having a delay of one or more full bit periods relative to the undelayed digital data signal. The number of delayed versions of the digital data signal with different delay that are combined together determine the so called order of pre-distortion. It is not known from this document that partial bit pre-distortion is equally well feasible by means of combining the digital data signal with a delayed version of it, the delay being set to p times the bit period. A typical value for p is 0.5, this being called half bit pre-distortion.
It is to be noted that the term bit in this context does not necessarily mean a unit of information or a data unit. Rather, in the context of pre-distortion this term generally refers to a repetitively at random occurring constant amplitude segment of minimum duration in the digital data signal. In the special case that the digital data signal format is binary providing two symbols represented by two different signal levels, one representing logic xe2x80x9c0xe2x80x9d and the other level representing logic xe2x80x9c1xe2x80x9d, then a segment of minimum duration has the same duration as a bit period. There exist, however, other well known digital data signal formats wherein a segment of minimum duration has a duration different from the duration of an information bit.
A conventional way to create the delayed digital data signal for combining with the undelayed digital data signal is to use a clock corresponding to the bit rate and clocked latches to delay the digital data signal by a given multiple or fraction of one bit period. This method is advantageous in that it can adapt to varying bit rates, but requires the existence of a bit rate synchronous clock. Another solution that does not require a bit clock signal is to apply a fixed delay to the digital data signal. This solution is simple but does not allow significant variations in the bit rate of the digital data signal.
An object of the present invention to provide a circuit and a method for providing a digital data signal with pre-distortion, the circuit and method allowing for variations of the data rate of the digital signal without there being a need for supplying a bit rate synchronous clock.
In accordance with the present invention a digital data signal is given a pre-distortion by means of combining the amplitudes of the digital data signal and of at least one delayed version of the digital data signal. The delayed digital data signal is provided by a delay circuit having an adjustable time delay. A circuit for detecting the duration of a signal pattern in the digital data signal that is indicative of the duration of a repetitively occurring signal segment that determines the delay appropriate in view of the current data rate of the data signal, generates an adjustment signal for adjusting the time delay provided by the adjustable delay circuit. In this way it is possible to add a full bit or partial bit pre-distortion of any desired order to the digital data signal even if the data rate of the digital data signal is unknown at the time of manufacturing the circuit for providing pre-distortion or is allowed to vary, without there being a need for a bit rate synchronous clock.
According to a preferred embodiment the detection of the duration of said signal pattern indicative of said minimum signal segment duration is accomplished by means of providing a delay locked loop that locks onto a predefined signal pattern of minimum duration in the digital data signal. The detected signal pattern can be a predefined sequence of symbols. In case the digital data signal format is binary, the signal pattern can be a simple sequence of alternating signal segments, e.g. pulses . . . xe2x88x92V,+V,xe2x88x92V . . . and/or . . . xe2x88x92V,+V,xe2x88x92V . . . or can be a more complex sequence like . . . xe2x88x92V,+V,xe2x88x92V,+V, . . . and/or . . . +V,xe2x88x92V,+V,xe2x88x92V . . . . It is evident that there exists a variety of possibilities for selecting signal patterns that can be used for detecting the minimum duration of signal segments in the digital data signal. Preferably, the detector circuit adjusts the delay of the delay circuit in accordance with the detected minimum signal pattern duration and refrains from adjusting the delay when similar signal patterns of longer duration occur in the digital data signal.
According to another preferred embodiment the detection of the duration of a repetitively occurring signal pattern in the digital data signal is accomplished by means of sampling the digital data signal at a sampling rate not less than the symbol rate, and detecting the minimum duration of signal segments in the digital data signal based on the minimum number of consecutive samples of the same amplitude. The delay adjustment signal is then generated depending on the detected minimum number of samples. Prior to sampling the digital data signal can be fed through a digital divider circuit that performs a frequency division by N, N being a positive integer greater than 1. In this case the sampling rate for the divided signal should be no less than the symbol rate of the digital data signal divided by N. The provision of a divider circuit is advantageous in that it lowers the speed requirements for the detection circuit, this being of particular importance when the data rate to be transmitted by the digital signal is high.
Preferably, the amount of delay of the digital data signal is made dependent on the symbol rate or data rate of the digital data signal such that the delay of the digital data signal expressed as a fraction of a bit period is larger for digital data signals having a high data rate than for data signals at a lower rate. In this way the amount of pre-distortion can even better match the frequency dependent loss characteristics of real world transmission lines over a large range of data rates.